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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
1/26 ? semiconductor MSM82C55A-2RS/gs/vjs general description the msm82c55a-2 is a programmable universal i/o interface device which operates as high speed and on low power consumption due to 3 m silicon gate cmos technology. it is the best fit as an i/o port in a system which employs the 8-bit parallel processing msm80c85ah cpu. this device has 24-bit i/o pins equivalent to three 8-bit i/o ports and all inputs/outputs are ttl interface compatible. features ? high speed and low power consumption due to 3 m silicon gate cmos technology ? 3 v to 6 v single power supply ? full static operation ? programmable 24-bit i/o ports ? bidirectional bus operation (port a) ? bit set/reset function (port c) ? ttl compatible ? compatible with 8255a-5 ? 40-pin plastic dip (dip40-p-600-2.54): (product name: MSM82C55A-2RS) ? 44-pin plastic qfj (qfj44-p-s650-1.27): (product name: msm82c55a-2vjs) ? 44-pin plastic qfp (qfp44-p-910-0.80-2k): (product name: msm82c55a-2gs-2k) ? semiconductor MSM82C55A-2RS/gs/vjs cmos programmable peripheral interface e2o0020-27-x3 this version: jan. 1998 previous version: aug. 1996 this product is not available in asia and oceania.
2/26 semiconductor MSM82C55A-2RS/gs/vjs circuit configuration group b port c (low order 4 bits) group a port c (high order 4 bits) group a port a (8) group b port b (8) group a control group b control data bus buffer read/ write control logic v cc gnd d 0 - d 7 8 rd wr reset cs a 0 a 1 8 8 8 8 8 4 4 8 8 4 4 8 pa 0 - pa 7 pc 4 - pc 7 pc 0 - pc 3 pb 0 - pb 7 internal bus line
3/26 semiconductor MSM82C55A-2RS/gs/vjs pin configuration (top view) 39 38 37 36 35 34 33 reset d 0 d 1 d 2. d 3 nc d 4 cs gnd a 1 a 0 pc 7 nc pc 6 18 19 20 21 22 23 24 pc 2 pc 3 pb 0 pb 1 pb 2 nc pb 3 6 5 4 3 2 1 44 rd pa 0 pa 1 pa 2 pa 3 nc pa 4 7 8 9 10 11 12 13 32 31 30 29 d 5 d 6 d 7 v cc pc 5 pc 4 pc 0 pc 1 14 15 16 17 25 26 27 28 pb 4 pb 5 pb 6 pb 7 43 42 41 40 pa 5 pa 6 pa 7 wr 44 pin plastic qfj 44 pin plastic qfp 16 15 14 13 pa 3 pa 2 pa 1 pa 0 rd cs gnd a 1 a 0 pc 7 pc 6 pc 5 pc 4 pc 0 pc 1 pc 2 20 19 18 17 pc 3 pb 0 pb 1 pb 2 pa 4 pa 5 pa 6 pa 7 wr reset d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 pb 7 1 2 3 4 5 6 7 8 9 10 11 12 40 pin plastic dip 32 31 30 29 28 27 26 37 38 39 40 36 35 34 33 25 pb 6 pb 5 pb 4 pb 3 24 23 22 21 v cc 33 32 31 30 29 28 27 reset d 0 d 1 d 2. d 3 d 4 d 5 cs gnd a 1 a 0 pc 7 pc 6 pc 5 12 13 14 15 16 17 18 nc pc 3 pb 0 pb 1 pb 2 v cc pb 3 44 43 42 41 40 39 38 rd pa 0 pa 1 pa 2 pa 3 v cc pa 4 1 2 3 4 5 6 7 26 25 24 23 d 6 d 7 v cc pb 7 pc 4 pc 0 pc 1 pc 2 8 9 10 11 19 20 21 22 pb 4 pb 5 pb 6 nc 37 36 35 34 pa 5 pa 6 pa 7 wr
4/26 semiconductor MSM82C55A-2RS/gs/vjs absolute maximum ratings C55 to +150 MSM82C55A-2RS supply voltage v cc C0.5 to +7 v input voltage v in C0.5 to v cc +0.5 v output voltage v out C0.5 to v cc +0.5 v storage temperature t stg c power dissipation p d 0.7 w parameter unit symbol ta = 25c conditions rating msm82c55a-2gs msm82c55a-2vjs 1.0 1.0 ta = 25c with respect to gnd operating range supply voltage v cc v t op range 3 to 6 C40 to 85 parameter unit symbol c operating temperature recommended operating range dc characteristics typ. supply voltage v cc 5v t op +25 "l" input voltage v il "h" input voltage v ih min. 4.5 C40 C0.3 2.2 max. 5.5 +85 +0.8 v cc + 0.3 parameter unit symbol c v v operating temperature typ. max. "l" output voltage v ol 0.4 v "h" output voltage v oh v v parameter unit symbol min. 4.2 3.7 i ol = 2.5 ma i oh = C40 m a i oh = C2.5 ma conditions v cc = 4.5 v to 5.5 v ta = C40c to +85c (c l = 0 pf) input leak current i li 1 m a output leak current i lo 10 m a C1 C10 0 v in v cc 0 v out v cc cs 3 v cc C0.2 v v ih 3 v cc C0.2 v v il 0.2 v supply current (standby) i ccs m a 8ma i/o wire cycle 82c55a-2 ...8 mhzcpu timing i cc average supply current (active) 10 0.1 msm82c55a-2
5/26 semiconductor MSM82C55A-2RS/gs/vjs ac characteristics min. max. setup time of address to the falling edge of rd t ar 20 ns hold time of address to the rising edge of rd t ra 0 ns parameter unit symbol remarks setup time of address before the falling edge of wr t aw 0 ns load 150 pf (v cc = 4.5 v to 5.5 v, ta = C40 to +85c) msm82c55a-2 delay time from the falling edge of rd to the output of defined data t rd 120 ns delay time from the rising edge of rd to the floating of data bus t df 10 75 ns time from the rising edge of rd or wr to the next falling edge of rd or wr t rv 200 ns rd pulse width t rr 100 ns hold time of address after the rising edge of wr t wa 20 ns wr pulse width t ww 150 ns setup time of bus data before the rising edge of wr t dw 50 ns hold time of bus data after the rising edge of wr t wd 30 ns delay time from the rising edge of wr to the output of defined data t wb 200 ns setup time of port data before the falling edge of rd t ir 20 ns hold time of port data after the rising edge of rd t hr 10 ns ack pulse width t ak 100 ns stb pulse width t st 100 ns setup time of port data before the rising edge of stb t ps 20 ns hold time of port bus data after the rising edge of stb t ph 50 ns delay time from the falling edge of ack to the output of defined data t ad 150 ns delay time from the rising edge of ack to the floating of port (port a in mode 2) t kd 20 250 ns delay time from the rising edge of wr to the falling edge of obf t wob 150 ns delay time from the falling edge of ack to the rising edge of obf t aob 150 ns delay time from the falling edge of stb to the rising edge of ibf t sib 150 ns delay time from the rising edge of rd to the falling edge of ibf t rib 150 ns delay time from the the falling edge of rd to the falling edge of intr t rit 200 ns delay time from the rising edge of stb to the rising edge of intr t sit 150 ns delay time from the rising edge of ack to the rising edge of intr t ait 150 ns delay time from the falling edge of wr to the falling edge of intr t wit 250 ns note: timing measured at v l = 0.8 v and v h = 2.2 v for both inputs and outputs.
6/26 semiconductor MSM82C55A-2RS/gs/vjs timing diagram basic input operation (mode 0) basic output operation (mode 0) wr cs , a 1 , a 0 t ww port output t dw t wb t aw t wa d 7 - d 0 t wd rd cs , a 1 , a 0 t rr d 7 - d 0 t hr t ir t ar t ra t rd t df port input strobe input operation (mode 1) stb intr t st rd port input t sib t sit t rit t ph t rib t ps ibf
7/26 semiconductor MSM82C55A-2RS/gs/vjs strobe output operation (mode 1) wr intr port output t wit obf t wob t wb t ak t ait t aob ack bidirectional bus operation (mode 2) t wob t st t sib t ps t ad t kd t ph t rib t aob t ak wr intr port a obf ack rd ibf stb
8/26 semiconductor MSM82C55A-2RS/gs/vjs output characteristics (reference value) 1 output "h" voltage (v oh ) vs. output current (i oh ) 0 1 2 3 4 5 0 C1C2C3C4C5 output current i oh (ma) output "h" voltage v oh (v) v cc = 5.0 v ta = C40 to + 85c 0 1 2 3 4 5 012345 output current i ol (ma) output "l" voltage v ol (v) v cc = 5.0 v ta = C40 to +85c 2 output "l" voltage (v ol ) vs. output current (i ol ) note: the direction of flowing into the device is taken as positive for the output current.
9/26 semiconductor MSM82C55A-2RS/gs/vjs pin description d 7 - d 0 item bidirectional data bus input and output pin no. input/output function cs chip select input input rd read input input a 0 , a 1 port select input (address) input pa 7 - pa 0 port a input and output pc 7 - pc 0 port c input and output these are three-state 8-bit bidirectional buses used to write and read data upon receipt of the wr and rd signals from cpu and also used when control words and bit set/reset data are transferred from cpu to msm82c55a-2. reset reset input input this signal is used to reset the control register and all internal registers when it is in high level. at this time, ports are all made into the input mode (high impedance status). all port latches are cleared to 0. and all ports groups are set to mode 0. when the cs is in low level, data transmission is enabled with cpu. when it is in high level, the data bus is made into the high impedance status where no write nor read operation is performed. internal registers hold their previous status, however. when rd is in low level, data is transferred from msm82c55a-2 to cpu. by combination of a 0 and a 1 , either one is selected from among port a, port b, port c, and control register. these pins are usually connected to low order 2 bits of the address bus. these are universal 8-bit i/o ports. the direction of inputs/ outputs can be determined by writing a control word. especially, port a can be used as a bidirectional port when it is set to mode 2. these are universal 8-bit i/o ports. the direction of inputs/outputs can be determined by writing a control word as 2 ports with 4 bits each. when port a or port b is used in mode 1 or mode 2 (port a only), they become control pins. especially, when port c is used as an output port, each bit can set/reset independently. gnd C C gnd wr write input input when wr is in low level, data or control words are transferred from cpu to msm82c55a-2. pb 7 - pb 0 port b input and output these are universal 8-bit i/o ports. the direction of inputs/outputs ports can be determined by writing a control word. v cc CC +5v power supply.
10/26 semiconductor MSM82C55A-2RS/gs/vjs basic functional description group a and group b when setting a mode to a port having 24 bits, set it by dividing it into two groups of 12 bits each. group a: port a (8 bits) and high order 4 bits of port c (pc 7 ~pc 4 ) group b: port b (8 bits) and low order 4 bits of port c (pc 3 ~pc 0 ) mode 0, 1, 2 there are 3 types of modes to be set by grouping as follows: mode 0: basic input operation/output operation (available for both groups a and b) mode 1: strobe input operation/output operation (available for both groups a and b) mode 2: bidirectional bus operation (available for group a only) when used in mode 1 or mode 2, however, port c has bits to be defined as ports for control signal for operation ports (port a for group a and port b for group b) of their respective groups. port a, b, c the internal structure of 3 ports is as follows: port a: one 8-bit data output latch/buffer and one 8-bit data input latch port b: one 8-bit data input/output latch/buffer and one 8-bit data input buffer port c: one 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input) single bit set/reset function for port c when port c is defined as an output port, it is possible to set (to turn to high level) or reset (to turn to low level) any one of 8 bits individually without affecting other bits.
11/26 semiconductor MSM82C55A-2RS/gs/vjs operational description control logic operations by addresses and control signals, e.g., read and write, etc. are as shown in the table below: setting of control word the control register is composed of 7-bit latch circuit and 1-bit flag as shown below. d 0 definition of input/ output of low order 4 bits of port c. 0 = output 1 = input definition of input/ output of 8 bits of port b. 0 = output 1 = input mode definition of group b. 0 = mode 0 1 = mode 1 definition of input/ output of high order 4 bits of port c. 0 = output 1 = input definition of input/ output of 8 bits of port a. 0 = output 1 = input mode definition of group a. d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 6 d 5 mode 0 0 mode 0 0 1 mode 1 1 mode 2 control word identification flag when set to 0, it becomes the control word for bit set/ reset. group a control bits group b control bits be sure to set 1 for the control word to define a mode and input/output. cs input 0 0 port a ? data bus 00 control 1 0 others 10 a 0 0 0 1 1 wr 1 0 0 1 operaiton operation a 1 output 0 1 1 0 rd 00 11 0 10 01 0 00 10 1 10 00 1 1 port b ? data bus port c ? data bus data bus ? port a data bus ? port b data bus ? port c data bus ? control register illegal condition data bus is in the high impedance status.
12/26 semiconductor MSM82C55A-2RS/gs/vjs precaution for mode selection the output registers for ports a and c are cleared to f each time data is written in the command register and the mode is changed, but the port b state is undefined. bit set/reset function when port c is defined as output port, it is possible to set (set output to 1) or reset (set output to 0) any one of 8 bits without affecting other bits as shown below. d 0 definition of set/reset for a desired bit. 0 = reset 1 = set d 1 d 2 d 3 d 4 d 5 d 6 d 7 control word identification flag when set to 1, it becomes the control word to define a mode and input/output. definition of bit wanted to be set or reset. dont's care d 3 d 2 port c 0 0 pc 0 0 0 pc 1 0 1 pc 2 d 1 0 1 0 0 1 pc 3 1 0 pc 4 1 0 pc 5 1 0 1 1 1 pc 6 1 1 pc 7 0 1 be sure to set to 0 for bit set/reset interrupt control function when the msm82c55a-2 is used in mode 1 or mode 2, the interrupt signal for the cpu is provided. the interrupt request signal is output from port c. when the internal flip-flop inte is set beforehand at this time, the desired interrupt request signal is output. when it is reset beforehand, however, the interrupt request signal is not output. the set/reset of the internal flip-flop is made by the bit set/reset operation for port c virtually. bit set ? inte is set ? interrupt allowed bit reset ? inte is reset ? interrupt inhibited operational description by mode 1. mode 0 (basic input/output operation) mode 0 makes the msm82c55a-2 operate as a basic input port or output port. no control signals such as interrupt request, etc. are required in this mode. all 24 bits can be used as two-8-bit ports and two 4-bit ports. sixteen combinations are then possible for inputs/ outputs. the inputs are not latched, but the outputs are.
13/26 semiconductor MSM82C55A-2RS/gs/vjs 1 1 d 7 1 1 1 1 1 1 2 1 type 3 4 6 5 7 8 1 1 1 1 1 1 1 1 0 0 d 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d 4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 d 3 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 d 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 d 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 output output port a output output output output output output input input input input input input input input output output high order 4 bits of port c output output input input input input output output output output input input input input output output port b input input output output input input output output input input output output input input input output control word group a group b low order 4 bits of port c output input input output ouput input input output output input input output output input 10 9 11 12 14 13 15 16 notes: when used in mode 0 for both groups a and b 2. mode 1 (strobe input/output operation) in mode 1, the strobe, interrupt and other control signals are used when input/output operations are made from a specified port. this mode is available for both groups a and b. in group a at this time, port a is used as the data line and port c as the control signal. following is a description of the input operation in mode 1. stb (strobe input) when this signal is low level, the data output from terminal to port is fetched into the internal latch of the port. this can be made independent from the cpu, and the data is not output to the data bus until the rd signal arrives from the cpu. ibf (input buffer full flag output) this is the response signal for the stb . this signal when turned to high level indicates that data is fetched into the input latch. this signal turns to high level at the falling edge of stb and to low level at the rising edge of rd . intr (interrupt request output) this is the interrupt request signal for the cpu of the data fetched into the input latch. it is indicated by high level only when the internal inte flip-flop is set. this signal turns to high level at the rising edge of the stb (ibf = 1 at this time) and low level at the falling edge of the rd when the inte is set. inte a of group a is set when the bit for pc 4 is set, while inte b of group b is set when the bit for pc 2 is set. following is a description of the output operation of mode 1.
14/26 semiconductor MSM82C55A-2RS/gs/vjs obf (output buffer full flag output) this signal when turned to low level indicates that data is written to the specified port upon receipt of the wr signal from the cpu. this signal turns to low level at the rising edge of the wr and high level at the falling edge of the ack. ack (acknowledge input) this signal when turned to low level indicates that the terminal has received data. intr (interrupt request output) this is the signal used to interrupt the cpu when a terminal receives data from the cpu via the msm82c55a-5. it indicates the occurrence of the interrupt in high level only when the internal inte flip-flop is set. this signal turns to high level at the rising edge of the ack (obf = 1 at this time) and low level at the falling edge of wr when the inte b is set. inte a of group a is set when the bit for pc 6 is set, while inte b of group b is set when the bit for pc 2 is set. mode 1 input (group a) pa 7 pa 0 - 8 inte a pc 4 pc 5 stb a ibf a pc 3 intr a rd (group b) pb 7 pb 0 - inte b pc 2 pc 1 stb b ibf b pc 0 intr b rd 8 note: although belonging to group b, pc 3 operates as the control signal of group a functionally. mode 1 output (group a) pa 7 pa 0 - 8 inte a pc 7 pc 6 obf a ack a pc 3 intr a wr (group b) pb 7 pb 0 - 8 inte b pc 1 pc 2 obf b ack b pc 0 intr b wr
15/26 semiconductor MSM82C55A-2RS/gs/vjs port c function allocation in mode 1 pc 0 pc 2 pc 3 combination of input/output group a: input group b: input pc 1 port c group a: input group b: output group a: output group b: input group a: output group b: output intr b intr b intr b intr b pc 4 pc 6 pc 7 pc 5 ibf b obf b ibf b obf b stb b ack b stb b ack b intr a intr a intr a intr a stb a stb a i/o i/o ibf a ibf a i/o i/o i/o i/o ack a ack a i/o i/o obf a obf a note: i/o is a bit not used as the control signal, but it is available as a port of mode 0. examples of the relation between the control words and pins when used in mode 1 are shown below: (a) when group a is mode 1 output and group b is mode 1 input. 1 1 1/0 0 1 0 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 as all of pc 0 - pc 3 bits become a control pin in this case, this bit is "don't care". control word selection of i/o of pc 4 and pc 5 when not defined as a control pin. obf a ack a intr a i/o pc 7 pc 6 pc 3 pc 4 , pc 5 pa 7 - pa 0 8 rd group a: mode 1 output group b: mode 1 input stb b ibf b intr b pc 2 pc 1 pc 0 pb 7 - pb 0 8 wr 2 1 = input 0 = output
16/26 semiconductor MSM82C55A-2RS/gs/vjs (b) when group a is mode 1 input and group b is mode 1 output. 0 1 1/0 1 1 0 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 selection of i/o of pc 6 and pc 7 when not defined as a control pin. stb a ibf a intr a i/o pc 4 pc 5 pc 3 pc 6 , pc 7 pa 7 - pa 0 group a: mode 1 input group b: mode 1 output obf b ack b intr b pc 1 pc 2 pc 0 pb 7 - pb 0 8 rd 2 1 = input 0 = output 8 8 2 wr 3. mode 2 (strobe bidirectional bus i/o operation) in mode 2, it is possible to transfer data in 2 directions through a single 8-bit port. this operation is akin to a combination between input and output operations. port c waits for the control signal in this case, too. mode 2 is available only for group a, however. next, a description is made on mode 2. obf (output buffer full flag output) this signal when turned to low level indicates that data has been written to the internal output latch upon receipt of the wr signal from the cpu. at this time, port a is still in the high impedance status and the data is not yet output to the outside. this signal turns to low level at the rising edge of the wr and high level at the falling edge of the ack . ack (acknowledge input) when a low level signal is input to this pin, the high impedance status of port a is cleared, the buffer is enabled, and the data written to the internal output latch is output to port a. when the input returns to high level, port a is made into the high impedance status. stb (strobe input) when this signal turns to low level, the data output to the port from the pin is fetched into the internal input latch. the data is output to the data bus upon receipt of the rd signal from the cpu, but it remains in the high impedance status until then. ibf (input buffer full flag output) this signal when turned to high level indicates that data from the pin has been fetched into the input latch. this signal turns to high level at the falling edge of the stb and low level at the rising edge of the rd .
17/26 semiconductor MSM82C55A-2RS/gs/vjs intr (interrupt request output) this signal is used to interrupt the cpu and its operation in the same as in mode 1. there are two inte flip-flops internally available for input and output to select either interrupt of input or output operation. the inte1 is used to control the interrupt request for output operation and it can be reset by the bit set for pc6. inte2 is used to control the interrupt request for the input operation and it can be set by the bit set for pc4. mode 2 i/o operation following is an example of the relation between the control word and the pin when used in mode 2. when input in mode 2 for group a and in mode 1 for group b. pa 7 pa 0 - 8 inte 1 pc 7 pc 6 obf a ack a rd pc 3 intr a pc 4 pc 5 stb a ibf a inte 2 wr port c function allocation in mode 2 pc 0 pc 2 pc 3 pc 1 port c confirmed to the group b mode pc 4 pc 6 pc 7 pc 5 intr a stb a ibf a ack a obf a function
18/26 semiconductor MSM82C55A-2RS/gs/vjs 1 1 1 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 as all of 8 bits of port c become control pins in this case, d 3 and d 0 bits are treated as "don't care". no i/o specification is required for mode 2, since it is a bidirectional operation. this bit is therefore treated as "don't care". when group a is set to mode 2, this bit is treated as "don't care". intr a obf a ack a stb a ibf a pc 3 pc 7 pc 6 pc 4 pc 5 pa 7 - pa 0 stb b ibf b intr b pc 2 pc 1 pc 0 pb 7 - pb 0 8 8 wr rd group a: mode 2 group b: mode 1 input
19/26 semiconductor MSM82C55A-2RS/gs/vjs 4. when group a is different in mode from group b group a and group b can be used by setting them in different modes each other at the same time. when either group is set to mode 1 or mode 2, it is possible to set the one not defined as a control pin in port c to both input and output as port which operates in mode 0 at the 3rd and 0th bits of the control word. (mode combinations that define no control bit at port c) when the i/o bit is set to input in this case, it is possible to access data by the normal port c read operation. when set to output, pc 7 -pc 4 bits can be accessed by the bit set/reset function only. meanwhile, 3 bits from pc 2 to pc 0 can be accessed by normal write operation. the bit set/reset function can be used for all of pc 3 -pc 0 bits. note that the status of port c varies according to the combination of modes like this. group a group b port c pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 1 2 3 4 5 6 7 8 9 mode 1 input mode 0 output mode 0 mode 0 mode 1 input mode 1 input mode 1 output mode 1 output mode 2 mode 0 mode 0 mode 1 input mode 1 output mode 1 input mode 1 output mode 1 input mode 1 output mode 0 i/o i/o ibf a stb a intr a i/o i/o pc 0 i/o obf a ack a i/o i/o intr a i/o i/o i/o i/o i/o i/o i/o i/o stb b ibf b intr b i/o i/o i/o i/o i/o ack b obf b intr b i/o i/o ibf a stb a intr a stb b ibf b intr b i/o i/o ibf a stb a intr a ack b obf b intr b obf a ack a i/o i/o intr a stb b ibf b intr b obf a ack a i/o i/o intr a ack b obf b intr b obf a ack a ibf a stb a intr a i/o i/o i/o controlled at the 3rd bit (d 3 ) of the control word controlled at the 0th bit (d 0 ) of the control word
20/26 semiconductor MSM82C55A-2RS/gs/vjs 6. reset of msm82c55a-2 be sure to keep the reset signal at power on in the high level at least for 50 m s. subsequently, it becomes the input mode at a high level pulse above 500 ns. note: comparison of msm82c55a-5 and msm82c55a-2 5. port c status read when port c is used for the control signal, that is, in either mode 1 or mode 2, each control signal and bus status signal can be read out by reading the content of port c. the status read out is as follows: group a group b status read on the data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 1 2 3 4 5 6 7 8 9 mode 1 input mode 1 output mode 0 mode 0 mode 1 input mode 1 input mode 1 output mode 1 output mode 2 mode 0 mode 0 mode 1 input mode 1 output mode 1 input mode 1 output mode 1 input mode 1 output mode 0 i/o i/o ibf a inte a intr a i/o i/o d 0 i/o obf a inte a i/o i/o intr a i/o i/o i/o i/o i/o i/o i/o i/o inte b ibf b intr b i/o i/o i/o i/o i/o inte b obf b intr b i/o i/o ibf a inte a intr a inte b ibf b intr b i/o i/o ibf a inte a intr a inte b obf b intr b obf a inte a i/o i/o intr a inte b ibf b intr b obf a inte a i/o i/o intr a inte b obf b intr b obf a inte 1 ibf a inte 2 intr a i/o i/o i/o 10 11 mode 2 mode 2 mode 1 input mode 1 output obf a inte 1 ibf a inte 2 intr a inte b ibf b intr b obf a inte 1 ibf a inte 2 intr a inte b obf b intr b msm82c55a-5 after a write command is executed to the command register, the internal latch is cleared in porta portc. for instance, 00h is output at the beginning of a write command when the output port is assigned. however, if portb is not cleared at this time, portb is unstable. in other words, portb only outputs ineffective data (unstable value according to the device) during the period from after a write command is executed till the first data is written to portb. msm82c55a-2 after a write command is executed to the command register, the internal latch is cleared in all ports (porta, portb, portc). 00h is output at the beginning of a write command when the output port is assigned.
21/26 semiconductor MSM82C55A-2RS/gs/vjs notice on replacing low-speed devices with high-speed devices the conventional low speed devices are replaced by high-speed devices as shown below. when you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. high-speed device (new) low-speed device (old) remarks m80c85ah m80c85a/m80c85a-2 8bit mpu m80c86a-10 m80c86a/m80c86a-2 16bit mpu m80c88a-10 m80c88a/m80c88a-2 8bit mpu m82c84a-2 m82c84a/m82c84a-5 clock generator m81c55-5 m81c55 ram.i/o, timer m82c37b-5 m82c37a/m82c37a-5 dma controller m82c51a-2 m82c51a usart m82c53-2 m82c53-5 timer m82c55a-2 m82c55a-5 ppi
22/26 semiconductor MSM82C55A-2RS/gs/vjs differences between msm82c55a-5 and msm82c55a-2 1) manufacturing process these devices use a 3 m si-gate cmos process technology. the msm82c55a-2 is about 7% smaller in chip size than the msm82c55a-5 as the msm82c55a- 2 changed its output characteristics. 2) function the above function has been improved to remove bugs and other logics are not different between the two devices. 3) electrical characteristics 3-1) dc characteristics as shown above, the dc characteristics of the msm82c55a-2 satisfies the dc characteristics of the msm82c55a-5. 3-2) ac characteristics item msm82c55a-5 msm82c55a-2 internal latch during writing into the command register only ports a and c are cleared. port b is not cleared. all ports are cleared. parameter symbol msm82c55a-5 msm82c55a-2 ''l'' output voltage 0.45 v (i ol = +2.5 ma) 0.40 v (i ol = +2.5 ma) 3.7 v (i oh = -2.5 ma) v ol v oh ''h'' output voltage 2.4 v (i oh = -400 m a) 8 ma maximum (i/o cycle = 375 ns) i cc average operating current 5 ma maximum (i/o cycle = 1 m s) parameter symbol msm82c55a-5 msm82c55a-2 address hold time for rd rising 20 ns minimum 0 ns minimum t ra rd pulse width 300 ns minimum 100 ns minimum t rr difined data output delay time from rd falling 200 ns maximum 120 ns maximum t rd data floating delay time from rd rising 100 ns maximum 75 ns maximum t rf rd/wr recovery time 850 ns minimum 200 ns minimum t rv
23/26 semiconductor MSM82C55A-2RS/gs/vjs as shown above, the msm82c55a-2 satisfies the characteristics of the msm82c55a-5. parameter symbol msm82c55a-5 msm82c55a-2 address hold time for wr rising 30 ns minimum 20 ns minimum t wa wr pulse width 300 ns minimum 150 ns minimum t ww data setup time for wr rising 1000 ns minimum 50 ns minimum t dw data hold time for wr rising 40 ns minimum 30 ns minimum t wd defined data output time from wr rising 350 ns maximum 200 ns maximum t wb port data hold time for rd rising 20 ns minimum 10 ns minimum t hr ack pulse width 300 ns minimum 100 ns minimum t ak stb pulse width 300 ns minimum 100 ns minimum t st port data hold time for stb falling 180 ns minimum 50 ns minimum t ph ack falling to defined data output 300 ns maximum 150 ns maximum t ad wr falling to obf falling delay time 650 ns maximum 150 ns maximum t wob ack falling to obf rising delay time 350 ns maximum 150 ns maximum t aob stb falling to ibf rising delay time 300 ns maximum 150 ns maximum t sib rd rising to ibf falling delay time 300 ns maximum 150 ns maximum t rib rd falling to intr falling delay time 400 ns maximum 200 ns maximum t rit stb rising to intr rising delay time 300 ns maximum 150 ns maximum t sit ack rising to intr rising delay time 350 ns maximum 150 ns maximum t ait wr falling to intr falling delay time 850 ns minimum 250 ns maximum t wit
24/26 semiconductor MSM82C55A-2RS/gs/vjs (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). dip40-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 6.10 typ.
25/26 semiconductor MSM82C55A-2RS/gs/vjs (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfj44-p-s650-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 2.00 typ. mirror finish
26/26 semiconductor MSM82C55A-2RS/gs/vjs (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.41 typ. qfp44-p-910-0.80-2k mirror finish

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